岗位职责
JD:ASIC或SoC芯片的模块级和顶层级物理设计;模块或芯片系统级电源地网络设计和验证;低功耗物理设计和验证;前后端时序优化,芯片级时序验证;模块和顶层版图物理验证,DRC/LVS/ERC等;完成netlist到GDSII的全流程工作:floorplan,powerplanning,place&route,cts,timingclosure,poweranalysis,physicalverification,ECO;Requirements:大学本科以上学历,微电子/电子工程/通信工程等相关专业;相关的IC后端设计工作经验或tape-out成功经验;熟悉PNR,STA,DRC,LVS、DRC等流程;熟悉EDA工具,如ICC2,Innovus,Primetime,Calibre,redhawk等;熟练使用tcl/perl/phython等;良好的英文沟通能力;公司简介:Foundedin2018,founderhas20years’ICindustryexperience,workedfortopICcompanieslikeIBM,AMD,Synopsys,Verisilicon,SYNAPSEandIntelasleader,haslong-term,solidandpositiverelationshipswithallpatterners.Andtheteammembersmosthave10+years’ICdesignexperience,mergingwiththefastestgrowingtechnologybothinASICandSOCfield,patternerincludingAMD,ADI,GlobalFoundries,HiGon,ZTE,GPT,SYNAPSE,MICROPILOT…Massproductionincludingdiverseproductions:7nm/14nmGPUdesignchip,28nmhigh-endgraphicchip,28nmmobilephonechip,28nmlow-powergraphicchip,40nmnetworkingchipset,55nmmobilechip…wealsoprovideprofessional,effectiveandpracticalconsultingservicefornewlyestablishedcompany.NowwehaveBeijing,Shanghai,Nanjing,Chengdusites,tosupportflexibleandhigh-efficiencyworkingmodelbothforpatternerandemployee.职能类别:数字后端工程师关键字:ICBackendphysicaldesign后端设计物理设计PNR
工作地址
成都-武侯区 (成都-武侯区-成都-武侯区) 查看地图
